| AMC510 |
Double Width
Full-Height |
Xilinx Virtex-5 FPGA in FF1136 package |
Option 144/288 MByte RLDRAM-II |
3 x SMA |
AMC.1
AMC.2
AMC.4 |
The AMC510 is an AMC FPGA Carrier so that it would allow custom mezzanine to be developed for different end applications. The module is compliant to the AMC.1, AMC.2 and/or AMC.4 specification. |
| AMC511 |
Single Width
Full-Height |
Xilinx Virtex-5 FPGA in FF1136 package |
Option 144/288 MByte RLDRAM-II |
7 x SMB |
AMC.1
AMC.2
AMC.4 |
The AMC511 is a Quad ADC (Analog to Digital Converter) module compliant to the AMC.1* and AMC.2 specification. The unit has an on-board, re-configurable FPGA which interfaces directly to the GbE or PCIe bus. The FPGA has an interface to the QDR-II memory (36 and 72-bit wide). |
| AMC513 |
Single Width
Full-Height |
Xilinx Virtex-6 FPGA in FF1759 package |
Option for up to 2GB of DDR-III memory |
1 x FMC |
AMC.1
AMC.2
AMC.4 |
The AMC513 is an AMC FPGA Carrier with an FMC (VITA 57) interface. The AMC513 is compliant to the AMC.1, AMC.2 and/or AMC.4 specification. The unit has an on-board, re-configurable FPGA which interfaces directly to the AMC Ports 2-3, 4-11, FCLKA, TCLKA, TCLKB, TCLKC, and TCLKD. |
| AMC530 |
Single Width
Full-Height |
Altera Stratix IV EP4S100Gx in 1517 pin count |
Option for up to 16GB of DDR-III memory to the FPGA |
2 x SPF+
1 x RJ45
2 x USB |
AMC.1
AMC.2
AMC.4 |
The AMC530 is an AMC FPGA module based on the Altera Stratix IV EP4S100Gx device. The AMC530 is compliant to the AMC.1, AMC.2 and/or AMC.4 specification. The unit has an on-board, re-configurable FPGA which interfaces directly to the AMC Ports 0-1, 2-3, 4-11, FCLKA, TCLKA, TCLKB, TCLKC, and TCLKD. |
| AMC514 |
Single Width
Full-Height |
Xilinx Virtex-6 FPGA in FF1759 package |
Option for up to 2GB of DDR-III memory |
1 x FMC |
AMC.1
AMC.2
AMC.4 |
The AMC514 is an AMC FPGA Carrier with an FMC (VITA 57) interface. The AMC514 is compliant to the AMC.1, AMC.2 and/or AMC.4 specification. The unit has an on-board, re-configurable FPGA which interfaces directly to the AMC Ports 2-3, 4-11, FCLKA, TCLKA, TCLKB, TCLKC, and TCLKD. The FPGA has an interface to four banks of DDR-III memory (32-bit wide). |
| AMC515 |
Single Width
Full-Height |
Xilinx Virtex-7 XC7V2000T in 1925 package |
Option for up to 2GB of DDR-III memory |
1 x FMC |
AMC.1
AMC.2
AMC.4 |
The AMC515 is an AMC FPGA Carrier with an FMC (VITA 57) interface. The AMC515 is compliant to the AMC.1, AMC.2 and/or AMC.4 specification. The unit has an on-board, re-configurable FPGA which interfaces directly to the AMC Ports 4-11, FCLKA, TCLKA, TCLKB, TCLKC, and TCLKD. The FPGA has an interface to a bank of DDR-III memory (64-bit wide). |
| FMC102 |
Single Width |
- |
- |
2 x GbE |
ANSI/VITA
57.1-2008 |
The FMC102 is an FPGA Mezzanine Module per VITA 57 specification. The FMC102 has two GbE PHY which allows 10/100/1000 Mbit to be routed via SERDES to the appropriate FMC pins. |
| FMC210 |
Single Width |
ADC converter e2v EV10AS150A |
- |
6 x MMCX |
ANSI/VITA
57.1-2008 |
The FMC210 is an FPGA Mezzanine Card per VITA 57 specification with a high speed ADC. The ADC converter utilizes the e2v part number EV10AS150A device which has a high linearity ADC. The module has a super low phase noise RF PLL Synthesizer for sampling. |
| FMC221 |
Single Width |
Single DAC converter Analog Devices AD9739 |
- |
6 x MMCX |
ANSI/VITA
57.1-2008 |
The FMC221 is an FPGA Mezzanine Module per VITA 57 specification. The FMC221 has a single DAC 14-bit at 2.5 GSPS. The DAC converter utilizes the Analog Devices AD9739. The FMC221 is designed for synthesizing of broadband signals, with enhanced linearity and band flatness performances. |
| FMC222 |
Single Width |
Dual DAC converter Analog Devices AD9739 |
- |
6 x MMCX |
ANSI/VITA
57.1-2008 |
The FMC222 is an FPGA Mezzanine Module per VITA 57 specification. The FMC222 has dual single DAC 14-bit at 2.5 GSPS. The DAC converter utilizes the Analog Devices AD9739. The FMC222 is designed for synthesizing of broadband signals, with enhanced linearity and band flatness performances. The two DAC are cable of synchronization with incoming data between the two. |
